The present invention relates to an improved electrostatic discharge (ESD) protection device for providing protections against high-voltage transients due to electrostatic discharge. More specifically, the present invention relates to an improved ESD protection device for use in integrated circuits to protect semiconductor devices from incurring damages because ofhigh-voltage transients due to electrostatic discharges. The ESD protection device present invention provides excellent robustness, does not require high voltage for triggering, and yet it is uniquely designed such that it is not vulnerable to being accidentally triggered due to non-ESD noises. Another advantage of the ESD protection device of the present invention is that it also provides an excellent flexibility to adjust the base width to optimize the breakdown behavior.
When a semiconductor device is brought in contact with an external electrostatic charge source (often designated as an input pad), an electrostatic discharge (ESD) will result. Semiconductor devices often have only a very small amount of series resistance between the input pad and the actual devices. When the input pad contains substantial amounts of electrostatic charges, the lack of series resistance associated with the semiconductor devices allows large amounts of electrostatic charges to pass through the circuitry for only a very short duration, resulting in very large voltage transients. Such an electrostatic discharge has proven in recent years to be a major cause contributing to the failures of a large number of semiconductor devices, and the integrated circuits containing the same.
U.S. Pat. No. 4,484,244 discloses ESD protection circuit systems utilizing one or more silicon control rectifiers (SCR) as transient protection structures in integrated circuits. Basically, these devices are bipolar devices each containing two SCR""s, one for protection from positive transient and another for protection from negative transients. Because these devices require a large number of diffused regions, they are compatible with semiconductors formed using metal oxide silicon technologies.
U.S. Pat. No. 5,012,317 discloses another ESD protection device which includes a PNPN type device disposed between an input pad and ground. For positive transients, a first P-region is disposed in an N-type well which, in turn, is formed in a P-type layer, and a second N-type region is provided for connection to the ground. This provides an SCR which can be turned on by avalanching an intermediate PN junction to place the device in a regenerative mode for positive transients. For negative transients, a P+ region is provided inthe P-layer to bypass the PN junction and a N+ region is defined in the N-type region to bypass another PN junction. This provides a forward-biased diode for the negative transients. The positive/negative bipolar ESD protection device has shown to provide excellent robustness, but it was found to be quite vulnerable to be accidentally turned on due to non-ESD-related triggering noises such as latchup.
The primary object of the present invention is to develop an improved electrostatic discharge (ESD) device for use in integrated circuits containing semiconductor devices. More specifically, the primary object of the present invention is develop an improved ESD protection device to protect semiconductor devices from incurring damages due to high-voltage transients. The ESD protection device of the present invention to be developed must exhibit excellent robustness under rugged conditions; it must also not require high triggering voltage. Furthermore, it must overcome the shortcoming of prior art devices such that it will not be accidentally triggered by a non-ESD noise such as latchup.
One of the key elements of the present invention is to implant a plurality of P+ regions in a floating N-type well (or xe2x80x9cN-wellxe2x80x9d), which is, in turn, formed in a P-type layer. These P+ regions are electrically connected to the input pad (i.e., the source of the electrostatic discharge). The ESD protection device of the present invention also contains a plurality of P+ regions that are connected to the ground, and an N+ region that is not grounded. The N+ region is formed in the P-type layer but outside the N-well. At least one of the grounded P+ region must be outside of the N-well (but still in the P-type layer). The rest of the grounded P+ region or regions can be in the N-well.
The combinations of (1) the plurality of the P+ regions in the N-well that are connected to the input pad, (2) the ungrounded N-well region, and (3) the grounded P+ regions in the N-well of the present invention form a plurality of open-base pnp bipolar transistors in the N-well. This is utilized to ensure that a low-voltage switching structure to turn on one of the pseudo bipolar structure of the present invention. The plurality of the pseudo pnp bipolar structures utilizing a common ungrounded N+ region prevent the ESD protection device of the present invention from being accidentally triggered by a non-ESD noise such as latchup, and turn on as a protection switch during an ESD event. The floating N-well is utilized to keep in off state regardless of whether the input signal is either positive or negative during normal operation conditions.
In summary, the present invention discloses an improved ESD protection device which comprises the following main elements:
(1) an N-type well formed in a P-type semiconductor layer;
(2) a plurality of first P+ regions formed in the P-type semiconductor layer, wherein each of the first P+ regions is connected to an input pad and is formed inside the N-type well;
(3) a plurality of second P+ regions formed in the P-type semiconductor layer, wherein each of the second P+ regions is connected to the ground and at least one of the second P+ regions is outside the N-type well; and
(4) an N+ region formed outside of the N-type well;
(5) whereby the plurality of first P+ regions, the plurality of second P+ regions, and the N+ region form a plurality of pnp devices in the N-type well to allow a transient voltage to be discharged from the input pad to ground.
As provided above, the multiplicity of the pseudo pnp structures provided in the ESD prevention device of the present invention allow the ESD device to be triggered without requiring a high voltage, while preventing it from being accidentally triggered by a non-ESD noise.